Responsibilities:
- Responsible for IP evaluation and integration.
- Responsible for scheme formulation, design implementation, simulation verification of module design.
- Responsible for chip architecture design and documentation.
- Responsible for providing technical support for application design and testing.
- Responsible for ASIC prototype verification using FPGA.
- Responsible for synthesizing the design using mainstream EDA tools, providing high-quality constraint files and Netlist to the backend.
Requirements:
- Bachelor's degree or above in electronics, communication, computer science and other related majors.
- Solid basic knowledge of digital circuit, proficient in Verilog HDL.
- Familiar with digital circuit timing design requirements, understand the chip design process.
- Good problem-solving skills, good communication skills and teamwork skills.